The vast majority of digital logic circuits require a clock signal to operate in cooperation with other circuits. This is especially true in modern telecommunications where signal sampling, channel feedback parameters, and information used to despread and decode a transmitted message are all highly dependent upon precise timing among devices. In the telecommunications realm, the changeover from analog to digital is generally described as moving the converter (analog to digital for transmitting, and digital to analog for receiving) as close as possible to the antenna, close meaning in the electronic pathway sense. As electronic sub-systems have become digitized, they are increasingly being integrated in fabricated circuit chips. Pure complementary metal-oxide semiconductor (CMOS) processes are becoming standard platforms for an increasing number of applications, including hardware for radio-frequency (RF) communications. Line-widths of the CMOS silicon processes continue to shrink as engineers learn to manipulate wafer fabrication with more precision. This results in more densely packed devices on a single chip, increasing electronic speed while decreasing physical size of implementing electronics and reducing chip costs.
One electronic bottleneck in RF ASICs has been generation of clock signals at a frequency less than that output by a high frequency oscillator. Many different processes within any individual electronic device—for example, sampling and decoding processes of a mobile station—must operate synchronously for seamless real-time communications. A single system clock is therefore desirable to maintain synchronous operation among the different sub-circuits, though those sub-circuits may operate at different clock speeds. Synchronous operation is obtained by dividing the system clock signal for those sub-circuits operating at less than the oscillator frequency. For example, co-owned International Patent Publication No. WO 00/31885, published on Jun. 2, 2000 and concerning RF signal processing in a radio telecommunication system, describes a divider that is used to divide a synthesizer signal so that received mixing signal corresponds to the selected frequency receive band. That reference is incorporated herein by reference for a particularly apt environment for the present invention, as detailed below. For example, a 4 GHz synthesizer may enable the same receiver to receive transmissions in the 2 GHz band or the 1 GHz band by dividing either by two or four, respectively. During transmission in the same system, that published application describes a similar function for a divider.
Analog dividers are known in the art, but occupy a large physical space and draw a large amount of power, both disadvantages for mobile telephony equipment. They often require some biasing to be functional, and are generally more sensitive to process variations. Conversely, classic digital dividers suffer from signal asymmetry, where the clock signal divider has outputs that are not balanced in phase (balanced being either matching or opposing phases). Digital clock dividers have also exhibited high noise, have imposed delays in signal processing, and typically draw a large current as compared to other more processing-intense circuits. For the above reasons, clock division continues to represent a bottleneck in the ‘digital revolution’.
One well-known prior art circuit 20 to digitally divide a clock signal is shown in FIG. 1. A clock signal 22 drives a clocked memory element 24 (CME). The CME 24 lies within a data loop 26 with an inverter 28. First 30 and second 32 output nodes along the data loop 26 are labeled 30 and 32, respectively. The CME is, for example, a flip-flop circuit, where the rising edge of the clock pulse causes the data bit stored in the flip flop to be output and the falling edge of the same clock pulse causes the next data bit to be input and stored within. The inverter is a simple logic gate, generally implemented in CMOS via transistors. The designator “M” represents the data bit stored in the CME 24 of FIG. 1. Assume high and low data states of 1 and 0, respectively, where an initial data bit (e.g., following a first falling edge of the clock) stored in the CME 24 is high (1). Upon the next rising edge of the clock, the high bit (1) is output from the CME 24 and lies on the first output node 30, and is input into the inverter 28 where it is changed to low (0) and output to lay on the second output node 32. At the next falling edge of the clock, the low bit (0) is input into the CME 24 from the second node 32, and the bits at the first 30 and second 32 nodes remain unchanged. At the next rising edge of the clock, the low data bit (0) from the CME 24 is output to the first node 30, and also inverted at the inverter 28 to lie on the second node 32 as a high bit (1).
The following truth table shows the above results and make clear that the output on either the first or second node is at one half the rate of the clock signal. By using several clocked memory elements 24, the division factor can be increased from 2 to any multiple of 2 (i.e. 4, 6, 8 . . . ). Odd divisions like 3, 5, 7 etc. can be-obtained by using more sophisticated feedback logic. However, there are inherent disadvantages to the circuit of FIG. 1. Following each of the rising edges of clock pulses, there is a delay in inverting node 30 with the inverter 28, resulting in the outputs at the first and second nodes (30&32) being out of phase with one another. (i.e. the first rising edge of the clock changes the 1st node from 0 to 1 and the second rising edge changes the 1st node from 1 to 0; and so on. So two rising edges of the input clock cause only one rising edge (0 to 1) at the output clock, which means that the output clock is divided by two.
Clock pulseCME1st node2nd nodeFirst Falling Edge1First Rising Edge10Second Falling Edge0Second Rising Edge01
What is needed in the art is a circuit and method to digitally divide a clock signal that is low in noise, low in power consumption, adaptable to divide the clock signal by any fraction, and that keeps a phase relationship between various outputs of the circuit. Such a circuit would be particularly advantageous if it also operated without imposing circuit delays in real time signal processing of mobile telecommunications, and if it were made from circuit devices already used and readily fabricated.